2019 Reports

Authors:  Yujia Wang, Peter McClure
Abstract: 
        Copper to copper bonding using copper sintering paste is a possible joining method for applications that operate at high temperatures and with high current densities such as power electronics. In this study, a sintering paste with ~85% nano- and micro- Cu particles in an organic binder was bonded onto copper coated silicon substrates. A domed shaped sample configuration allowed for effective evaluation of final sinter quality as a function of processing conditions. The effects of process variables such as formic acid exposure time, vacuum level, vacuum time, and paste volume on the copper sintering behavior (sintered density, porosity, interfacial bonding) were investigated. It was found that low vacuum pressure with long vacuum times could increase sintering density and that a formic acid environment was needed for adequate sintering but could be detrimental in over abundance.
Key words: Sintered Cu, Cu-Cu bonding, Reducing atmosphere, Formic acid, Tube furnace


Localized Laser Reflow of Through-Hole Electrolytic Capacitors
Author: Luke Wentlent
Abstract:
        Because of their process temperature limitations, aluminum electrolytic capacitors are often specified with a leaded through-hole format and attached to circuit boards using either a wave solder process or hand soldering.  This is particularly true when Pb-free solder assembly is required, essentially ruling out surface mount soldering of these devices.  An prototype laser reflow tool developed in the UIC Advanced Process Lab was used demonstrate Pb-free solder attachment of leaded electrolytic capacitors using dispensed solder paste and area selective laser reflow.  Soldering was accomplished with minimal temperature rise of the capacitor body.  Such an automated laser reflow process shows considerable promise for eliminating the added cost of hand soldering or wave soldering while improving the field reliability of the capacitors through dramatic reduction in process temperature exposure.
Key words:  laser reflow, electrolytic capacitor, Pb-free solder, area selective laser 


Copper Sintering of Copper Pillar WLCSPs: Role of Pressure, Atmosphere, and Peak Temperature/Time
Author: Peter McClure
Abstract:
        Copper sinter bonding could be a key enabler of 3D die stacking, high power electronics, and high temperature electronics. If sufficient sintering can be achieved, copper sintered bonds could provide high mechanical strength, thermal conductivity, electrical conductivity, and resistance to damage from high currents. Copper sintering paste was used to bond copper pillar chips to substrates in a tube furnace at different temperatures, pressures, and environments of formic acid and nitrogen. Resulting sintered copper bonds were examined in cross section for integrity of interfacial bonding, density of sinter, and overall joint morphology. The effects of sintering pressure, temperature, and environment on the final sintered copper bonds formed between copper pillars and a copper covered Si substrate were examined.
Key words: Copper sintering, formic acid, copper pillar, tube furnace, sinter, copper nano-paste


Indium Thermal Interfaces:  Metallographic Preparation and the Role of Bonding Metallization
Authors:  Yujia Wang, Peter McClure
Abstract
        Indium has gained attention as a die level thermal interface material (TIM) for high-power electronics due to its high thermal conductivity and mechanical compliance. However, there is minimal microstructural understanding of the indium system as it is difficult to analyze. Components containing indium are difficult to cross-section; conventional mechanical polishing is considered impossible, so slow and expensive focused ion beam (FIB) techniques are required [1,2]. In this study, a metallographic preparation procedure for components with indium was developed based on mechanical polishing, ultrasonic cleaning, etching, and ion milling. Packages with indium TIM layers and either Au or Ag metallized Si chips with Cu heat spreader lids were examined. Intermetallic compounds between In-Au, In-Ag, and In-Ni were investigated through energy-dispersive X-ray spectroscopy (EDS). The effects of bond metallization, doping, and solder reflow cycles on the microstructures were examined.
Key words: TIM, Indium, Cross-section technique, Etching, Ion-milling


Drop Shock Evaluation of SAC305 BGA Assembled with BiSnAg Low Melt Solder Paste
Authors: Xuanyi Ding, Michael Meilunas, Luke Wentlent  
Abstract
        BGA components with SAC305 solder balls were assembled using either SnAgCu or low-melting point BiSnAg solder pastes. The assembled samples were then subjected to repeated mechanical shock testing using a drop table. Samples were dropped at various table accelerations ranging from 500 to 900G. A lifetime analysis was then performed using Weibull distribution plots with selected samples being subjected to failure analysis to observe the failure mode.
        The test results showed that the samples assembled with the low-melting point BiSnAg solder paste did not perform as well in drop testing as the SnAgCu assembled samples for all test conditions evaluated. Failure analysis would show that the BiSnAg assembled populations generally failed due to repetitive crack growth near the printed circuit board pad intermetallic region where the bismuth phases resided. Likewise, the SnAgCu samples failed due to progressive solder joint cracking near the printed circuit board intermetallic region, but electrically functional SnAgCu joints with partial solder cracking and partial pad cratering were also observed.


Authors:  Luke Wentlent, Michael Meilunas 
Abstract
        Lead-free solder alloys containing high bismuth concentrations have been developed for low-temperature reflow assembly. These alloys are available in solder paste form and may possibly be used to assemble electronic components using reflow temperatures as low as 150˚C as measured at the solder joint positions. Although the process procedures required to create such assemblies are straightforward, the reliability performance of the bismuth bearing alloys is not well documented and requires significant study before the materials can be adopted by industry. This concern is compounded by the fact that the microstructural characteristics of the bismuth based alloys are highly dependent upon processing parameters such as temperature, time and solder paste volume when assembled in a “mixed” alloy system (i.e., used with SnAgCu bearing components). It is hypothesized that such microstructural variability may significantly impact the thermomechanical reliability of the assemblies. 
        The experiment described in this report is a first-pass reliability analysis of lead-free surface mount componentry assembled using near-eutectic tin-bismuth based solder pastes. To that extent, ten lead-free daisy-chained surface mount component designs including BGA and QFN were assembled to printed circuit boards with either SnBi or SnBiAg solder pastes using forced convection reflow processes of 200˚C or lower peak solder joint temperatures. The samples were inspected after assembly using x-ray imaging and selective cross-sectional analysis. Test vehicles were then subjected to accelerated thermal cycling with in-situ monitoring in order to stress the assemblies in an attempt to generate solder joint fatigue failure. Failure rate data was then compiled and compared using Weibull distribution plots. 
        The experimental results indicate that the paste selection and reflow processes had a significant impact on package reliability, however no definitive trends were observed. Instead, the failure rate results indicate that each component evaluated had a unique response to the assembly parameters resulting in instances where a certain set of process parameters could produce the best reliability with one component while the same process parameters resulted in the lowest reliability for another component. Fortunately, the overall reliability performance of the SnBi assemblies tested were quite good, with many test cells capable of surviving over 1000 cycles of -40 to 105˚C accelerated thermal cycling without failure, indicating that the low-melt SnBi alloys may still be of practical use in many applications. 
        At this time, the reason for such variability in reliability response is not well understood and further study of the SnBi alloys is underway. Due to the numerous variables evaluated and complex solder behaviors, the bulk of the microstructural and failure analysis results from this experiment will be addressed in a separate, upcoming report.   

Effect of Surface Roughness on TIM Thermal Resistance
Authors:  Peter McClure, Michael Gaynes
Abstract
        To examine the effect of surface finish on the thermal performance of thermal interface materials (TIMs), various surface finishes were tested with four different TIMs to find trends in thermal resistance as surface finish changed from rough to smooth. A grease, putty, soft pad, and stiff pad TIM were all tested against five different surface finishes. The TIMs selected represented different categories of TIMs with a variety of mechanical compliances. The roughness used represented possible surfaces encountered on heat sinks and thermal lids, from rough machined surfaces to polished metal. General trends for smoother surfaces producing lower thermal resistance were seen but outliers were significant and common. So application specific testing would be needed for any TIM/surface finish interaction of interest.
Key words: thermal interface material, TIM, roughness, thermal rod tester, thermal grease, thermal putty, thermal pad


Evaluating the Stability of Thermal Putties and Pads at Thin Bond Lines Using Electrical Capacitance
Authors:  Michael Gaynes, Peter McClure
Abstract
        The durability of thermal interface materials in large complex printed circuit board (PCB) assemblies is difficult to model and therefore, experimental study and verification is needed. In this study, the thermal mechanical stability of dielectric thermal interface materials is monitored using electrical capacitance, the inverse of which has the same geometric dependence on bond line and area as thermal resistance. Electrical capacitance is a straightforward, fast and accurate measurement method which can be used with mechanically representative hardware very early in the development cycle. This study includes two thermal cycle tests of 500 cycles between 0 and 100 ⁰C each with four thermal interface materials (TIMs) on hardware that is easily prototyped and mechanically representative of large complex PCBs. Electrical capacitance of the TIMs was measured in situ during thermal cycle testing and was able to distinguish both stability and degradation. Analysis of the TIMs after the test confirmed structural degradation in the form of cracks, material movement and delamination. In summary, electrical capacitance has broad application in evaluating the stability of dielectric TIMs in application specific designs very early in development by using easily procured mechanically representative hardware.


Self-Assembly Anisotropic Conductive Paste Evaluation:  Excess Material and Joint Structure
Authors:  Yujia Wang, Peter McClure
Abstract
        Anisotropic conductive pastes that can self-assemble have been gaining attention in the electronics packaging industry due to their potential applications as interconnect materials. These pastes are epoxy resin systems heavily loaded with metal particles. During heating, the metal particles agglomerate to form joints, attaching components to circuit boards. Potential advantages of these pastes are simplified processing procedures, forming joints and partial underfills simultaneously, and flexibility in accommodating different board designs [1]. However, under some process conditions, the pastes may form weak solder joints with poor mechanical/electrical conductivity or have excess metal particles outside of joints and cause electrical shorts. Therefore, effects of different process variables on the self-assembly behaviors of the paste need to be evaluated. In this study, a Self-Assembly Anisotropic Conductive Paste (SAP) with 50-70wt% SnBi particles in epoxy resin was evaluated. Effects of different process variables such as heating profile, solder mask design, and paste volume on the self-assembly procedures and joint structure were examined to gain insight into the paste. The self-assembly procedure was monitored with in-situ observation, structures of solder joints were examined by cross-sectioning, and potential factors related to the self-assembly are discussed.
Key words: Self-Assembly, SnBi, Underfill, Flexible Substrate, SAC, WLCSP, Low Melt Solders


Area Selective Laser Reflow:  Accelerated Thermal Cycle Reliability
Authors:  Luke Wentlent, Michael Meilunas
Abstract
        The thermal cycle reliability consequences of a surface mount laser reflow assembly process are investigated for two package types believed most suitable for laser assembly: wafer level chip scale packages (WLCSP) and surface mount resistors (SMR). These device types readily transmit the impinging laser energy to the forming solder joints. WLSCP49, WLCSP116 and SMR2512 devices are assembled to a test board using either area laser selective reflow or forced convection mass reflow. Either SAC305 or eutectic SnPb solder pastes are used with the latter producing mixed solder joints for the two SAC305 bumped WLSCP devices. Seven experimental test cells are assembled and subjected to accelerated thermal cycling (ATC) with a -40/125°C temperature profile. This report describes assembly observations from the various process combinations and insight from detailed evaluation of the associated ATC reliability performance and solder joint failure mechanisms.


TB2019-U Test Vehicle: Board and Components
Author:  Pericles A. Kondos
Abstract: 
        A special board was designed to study the effect of corner/edge bonding and/or capillary underfilling on the Accelerated Thermal Cycling (ATC) reliability of a variety of assembled BGA-type components. These include a large fine pitch BGA. The details of the PCB and of the components are presented in this report.


QFN Power Cycle Reliability Testing
Authors: Michael Gaynes, Michael Meilunas
Abstract:
        The Quad Flat No-Lead Package (QFN) is a low cost, near chip scale package with electrical and thermal performance advantages due to short wirebond length and an exposed copper lead frame. However, the no-lead perimeter lands on the bottom of the package result in a low stand-off solder interconnect that has shorter fatigue life compared to traditional quad flat packs with leads.
        In Information Technology hardware applications, during periods of low operational traffic, chip power is conserved by going to an idle state. Consequently, many power-on/idle cycles accrue. Unlike traditional thermal cycle testing, a power-on state heats the chip internally and heat is transferred from the chip to its surrounding packaging materials that include the solder joints. Moreover, power-on cycles accumulate in the tens of thousands of cycles.
        Power cycle testing was completed on a 12 x 12 mm QFN package where the target power-on chip temperature was 130 ⁰C resulting in a corner solder joint temperature of 80 ⁰C. The QFN package was solder attached to a 3 mm thick printed circuit board on sites with and without thermal vias. The solder voiding between the QFN lead frame thermal pad and thermal pad on the PCB has typically >40% as expected from industry experience. Finite element analysis was used to show that only a small percent of solder area coverage of the thermal pad is needed to benefit from the thermal vias in the PCB which reduce thermal resistance significantly compared to no thermal vias. The solder connection from the QFN thermal pad to a PCB thermal pad is only of benefit if thermal vias are present.  Twelve QFNs were power cycled out to >31,000 cycles. Three parts failed with typical bulk fatigue in the corner solder joints. Only one of these fails was relevant. A runaway chip temperature on the other QFNs negated any reliability assessment. However, the one relevant failure occurred before the chip temperature increased inordinately and therefore, indicates a reliability concern and the need for continued study.
Key words: QFN, power cycle
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