2018 Reports

System in Package: Alternative Solder Alloy Reliability
Author: Michael Meilunas
        Multiple system in package (SiP) assemblies housing two testable CSP configurations were provided to the AREA Consortium for reliability analysis. The SiP modules were identical in design but were assembled with six different combinations of CSP component solder bump and solder paste alloys. The samples were subjected to accelerated thermal cycling and monitored until failure. Lifetime analysis was then performed using Weibull distribution plots and selected samples were subjected to failure analysis. The results of the experiment indicated that both the solder bump and solder paste alloys could significantly impact the thermal cycle performance of the CSPs, but the effect varied depending upon the CSP configuration in the SiP. In relative terms, the performance of the low reliability CSP configuration was significantly impacted by solder ball alloy while the performance of the high reliability CSP configuration was significantly impacted by the solder paste alloy.

Flipchip Joining to Temperature Sensitive Flexible Substrates Using a Die Bonder with Asymmetric Heating
Authors:  Peter McClure, Mukund Ayalasomayajula
        Being able to join bumped silicon chips to temperature sensitive flexible substrates is a key manufacturing enabler for the flexible hybrid electronics industry. Attachment of such devices using asymmetric heating applied with a die bonder was explored as a means to minimize the thermal load on temperature intolerant substrates. Chip joining with SnAgCu (SAC) solder, BiSnAg solder, and an isotropic conductive adhesive material were all demonstrated through the use of top side asymmetric heating. Polyimide, polyethylene terephthalate, and thermoplastic polyurethane substrates were examined for physical or chemical alteration from the thermal load of such bonding.
Key words: Asymmetric heating, PI, PET, TPU, ICA, BiSn, SAC, Die Bonder
        With ever increasing power density in electronic packages, thermal management is critical to ensure reliable device operation within specification temperatures. Efforts are made to transfer heat efficiently between the heat source and the heat sink by reducing the thermal resistance. Thermal interface materials (TIMs) improve the efficiency of heat transfer by filling in between the asperities and air gaps of these two mating surfaces. In this study, four leading edge chip level TIM1s were evaluated. Characterization included measurement of unit area thermal resistance and thermal conductivity on metal rod samples.  Hardware performance was evaluated using two types of flip chip modules.  Thermal test chips were used to assemble test vehicle modules and Intel® Core™ i3 6100 functional processor modules were disassembled and rebuilt, with the four selected TIM1s as the thermal solution. The TIM1  was applied between the flip chip and the nickel plated, copper heat spreader. Thermal resistance was measured at time zero. Post assembly mechanical integrity of the thermal interface material was investigated using C-SAM (C-mode Scanning Acoustic Microscopy), cross-sectional analysis and SEM/EDX (scanning electron microscopy with energy dispersive x-ray). Improvement in time zero performance is reported for rebuilt processors compared to the existing thermal solution in Intel processors. Further process development is needed to optimize assembly process conditions for time zero and reliable thermal performance. 

Assessment of BiSn/SAC Mixed Assemblies: Microstructure and Strain Rate Sensitivity 
Author:  Luke Wentlent
        The continued push of the electronics packing industry for less damaging reflow techniques has resulted in an increased interest in low-melting point solder alloys. While solder systems, such as eutectic Bi-Sn, offer significantly lower melting points (~139°C) they are not commonly used in the industry and there is a considerable deficit of reliability and mechanistic knowledge. Additionally, most BGA components come balled with SnAgCu solder spheres as it is the current industry standard. When low temperature BiSn eutectic paste is used in conjunction with the SAC, a mixed solder joint is formed of which the reliability and performance is relatively unknown. This study takes a first look at the reliability behavior of the BiSn(Ag)/SAC mixed assembly solder joints and identified the failure mechanisms and behaviors in accelerated thermal cycling.

VIPPO Type Failures in PCBs with Buried Vias 
Author:  Pericles Kondos
        A board with long buried vias in different locations relative to nearby pads was used to study a defect manifesting itself as a clean separation between the solder and the intermetallic layer of one of the pads (usually at the component side) after a second reflow, leaving a relatively smooth solder-side failure surface not mirroring the shape of the intermetallic. Because this defect has often been observed in PCBs that have a mixture of Via-in-Pad-Plated-Over (VIPPO) and non-VIPPO pads, it has been designated “the VIPPO defect”. It was found that the buried via location affected the incidence frequency of this defect as did some process parameters including the reflow atmosphere (air vs. nitrogen). One of these combinations seemed to have the best chance of completely eliminating the defect, although more experiments are needed to verify this conclusion.

BGA Reliability as a Function of PCB Pad Geometry
Author:  Michael Meilunas 
      Three daisy-chained Ball Grid Array (BGA) package designs were assembled to printed circuit boards (PCB) containing solder mask defined (SMD) and non-solder mask defined (NSMD) pad geometries using SnPb and SAC305 soldering processes. The samples were subjected to accelerated thermal cycling with in-situ monitoring in order to stress the assemblies in an attempt to generate solder joint fatigue failure. Failed specimens were then analyzed in order to determine failure mode and location and lifetime data was compiled and compared using Weibull plots.  The experimental results indicate that circuit board pad definition is an important factor affecting Ball Grid Array solder joint lifetime. Interestingly, the relative reliabilities of the BGA assemblies on SMD and NSMD PCB pads were found to be dependent upon both component selection and solder alloy.    

FEA of BGA Joint Stress as a Function of Die Size 
Authors:  Mahdi Farahikia, Peter McClure, Richard Coyle, Jim Wilcox
        Finite Element Analysis (FEA) was conducted to gain insight into stresses occurring during accelerated thermal cycling (ATC) in a large silicon die ball grid array (BGA) package.  This BGA package has exhibited a variety of atypical behaviors in previous studies.  For example, studies have reported failures in package corner joints as expected but with bimodal cracking along the printed circuit board (PCB) side of the joint.  When non-corner joints failed however they exhibited more traditional cracking along the component side of joint.  Beyond the cracking behavior, some studies have reported unexplained increased ATC lifetime with thermal aging.  These BGAs where built with abnormally large Si die to drive quicker failures in ATC testing.  It was thought that atypical stresses associated with this large die could be driving the unexpected failures/results.  To test this, a study compared this package under ATC with three different die sizes.  All die sizes exhibited the abnormal corner joint failure modes but the smaller die BGAs had an increased occurrence of non-corner joint failures with traditional cracking.  These results pointed to stresses changing with die size and possibly causing the atypical corner joint failures.  This study used FEA to examine the stresses in solder joints as a function of die size and joint location.  By modeling the three different die size packages under thermal cycle it was found that the atypical failure in corner joint correlated to large normal stress ranges seen in only in corner joints.  Additionally, increased die size was found to increase the relative stress concentrations of the normal stress range in corner joints; possibly correlating with the increase in non-corner joint cracking seen with smaller die.  

Key words:  FEA, BGA, Die Size, ATC, Normal Stress Range

        Ten large BGA (60mm) System in Package (SiP) configurations were evaluated for assembly issues and thermal cycle reliability performance. Dynamic warpage was characterized using Shadow Moiré interferometry and the shape profiles were used to analyze assembly yield defects.  Samples were subjected to -40 to 125C thermal cycling in order to stress the assemblies and drive solder fatigue failures for comparative reliability analysis. Failure locations were mapped for all configurations and select samples were cross-sectioned to examine failure mode. Weibull analysis was performed on all SiP BGA and CSP populations in an attempt to correlate reliability to SiP layout. The results of this experiment showed that memory placement, solder alloy, and underfill application all significantly impact the SiP BGA reliability.