2018 Reports

Authors:  Faramarz Hadian, Mohammed Genanu, and Eric Cotts
Abstract:
        Industry interest has been growing in Sn based solders containing Bi, including SnAgCu (SAC) solder with a few percent added Bi, as well as SAC/Sn57Bi1Ag mixed assemblies. The mechanical properties of Sn-Bi alloys vary dramatically with Bi concentration. The strength doubles with the addition of up to approximately three percent Bi, then decreases by approximately 25% as the Bi concentration increases to that of the eutectic. Moreover, the ductility of SnBi alloys, as reflected in elongation measurements, varies substantially with Bi concentration, decreasing dramatically with the addition of a few percent of Bi and displaying maximum values between 30 and 40% Bi. Variations in Bi concentration can thus profoundly affect the mechanical properties of Sn based alloys. Processes which affect the distribution of Bi atoms in Sn based solder joints therefore needs to be better understood. Electrical current stressing has been shown to be very effective in promoting Bi diffusion in Sn. This study examines the effect of current stressing on the distribution of Bi atoms in SAC/Sn-57Bi-1Ag mixed assemblies. The evolution of the microstructures of SAC/SnBiAg mixed solder joints were studied under current stressing at elevated temperatures and extended times.  Certain conditions resulted in the clear segregation of a significant amount of Bi. Results of a simple model used to obtain the product of diffusivity and effective charge number were consistent with previous measurement of the diffusion of Bi in Sn. 


Finite Element Analysis of Ultra-Thin Die Ejection from Wafer Dicing Tape
Authors: Peter McClure, Preeth Sivakumar, Jesus Espinosa
Abstract:
        Finite element analysis (FEA) was used to examine the stress in thin Si die during pin assisted ejection from wafer dicing tape. Ultra-thin die (<75µm) are becoming more prevalent for use in flexible electronics, space saving, and die stacking. Due to the flexible and brittle nature of thin die, picking die directly from dicing tape for placement on a board is especially difficult. FEA was used to examine ways to minimize stress in such thin die during ejection from wafer tape. Digital image correlation (DIC) measurements were done with an ultra-thin wafer for calibrating the FEA model. Finite element simulations allowed for examining the role of various design parameters on a successful die eject and pick without the use of expensive and time consuming experimental testing. 
Key words: Ultra-thin die, wafer dicing tape, FEA, DIC, die ejection

Removing Solder Voids from BGA Assemblies Using Convective Vacuum Reflow
Author:  Michael Meilunas
Abstract: 
        Ten printed circuit board assemblies containing 0.8mm and 1.0mm pitch BGA components were provided to the AREA Consortium. The boards had been previously assembled using a standard convective reflow process and post-assembly inspection had found that specific BGA solder joint locations contained an unusually high number of small voids. The boards were subjected to a second reflow pass at Universal Instruments using an in-line convective vacuum oven to evaluate the effectiveness of vacuum reflow for removal of the unusual voids. X-ray inspection and data analysis was performed before and after vacuum reflow on the joints of interest and on “normal” joints for comparative analysis. The results of the experiment indicated that the vacuum reflow generally reduced cumulative voiding at the joints of interest while slightly increasing or decreasing voiding at the “normal” joint positions. Furthermore, vacuum reflow was found to generate solder joint bridges which were likely due to pre-existing void expansion when the environmental pressure was reduced.

Soldering to Printed Ink Circuitry:  Preliminary Exploration
Authors: Peter McClure and Mukund Ayalasomayajula
Abstract:
        Being able to bond integrated circuits to conductive ink circuity is a key enabler for flexible electronics and 3D printed electronics. Most commonly printed ink circuitry has been used simply to carry current and/or signal along a free surface such as a flex cable. It is not often directly bonded to semiconductor devices. As ink circuitry usage grows and more computationally complex applications arise, the capability for bonding die directly to ink circuits becomes necessary. To date, bonding to ink has been primarily done with conductive adhesives. While adhesives offer some ease of manufacturing they are not as electrically conductive as solder and can have handling difficulties. In this work tin silver copper (SAC) solder and bismuth tin silver (BiSnAg) solders are used to bond bumped chips to ink circuitry. Solder joint microstructures and general properties are examined and compared to isotropic conductive adhesive joints. Two types of inks were examined: a copper based solderable ink and a silver based ink. Initial findings are presented along with factors to consider when bonding to ink circuitry.
Key words: Solderable ink, Copper ink, Silver ink, SAC, BiSnAg, ICA, Flexible Substrates


Solder Joint Void Analysis of Surface Mount Components Assembled using an In-line Vacuum Reflow Oven 
Authors: Michael Meilunas and Arvind Srinivasan Karthikeyan
Abstract: 
        An in-line convection reflow oven consisting of 10 forced-air heating zones followed by an integrated heated vacuum chamber and controlled cooling unit was used to study vacuum application on the quality of surface mount component solder joints. Through iterative trials the oven was used to evaluate the effects of evacuation rate, vacuum pressure level and vacuum hold time on the solder joints of a number of surface mount devices including QFN, LGA, WLCSP, and SMR. Other factors such as reflow atmosphere (Air or Nitrogen), solder paste selection, and printed circuit board finish (Immersion Tin or ENIG) were then compared using the optimum process conditions established for the test vehicle. Results were also compared to a standard in-line convection reflow process using identical test assemblies. The results of this experiment indicate that the application of vacuum can both positively and negatively impact solder joint quality and assembly yield and the results are highly dependent upon the package type and the process factors of evacuation rate and vacuum pressure level.


Assessment of Selective Laser Reflow Technology for SMT Rework
Author: Luke Wentlent
Abstract: 
        A significant challenge of the SMT rework process is localizing the heat enough so that only the component or package of interest is brought to reflow temperatures. With the increasing complexity and package density of most modern electronics, especially mobile and server applications, this becomes an even more significant issue. One potential solution to this temperature management challenge is to apply the heat to the area of interest by using a mid-IR laser beam. This would effectively allow for a well-defined region to be heated with very minimal spillover to the rest of the PCB. The general effectiveness of this concept was explored using a Laser Rework instrument and a variety of SMT sample assemblies. Assessments of the effectiveness of this technique and associated challenges were made.


System in Package: Alternative Solder Alloy Reliability
Author: Michael Meilunas
Abstract
        Multiple system in package (SiP) assemblies housing two testable CSP configurations were provided to the AREA Consortium for reliability analysis. The SiP modules were identical in design but were assembled with six different combinations of CSP component solder bump and solder paste alloys. The samples were subjected to accelerated thermal cycling and monitored until failure. Lifetime analysis was then performed using Weibull distribution plots and selected samples were subjected to failure analysis. The results of the experiment indicated that both the solder bump and solder paste alloys could significantly impact the thermal cycle performance of the CSPs, but the effect varied depending upon the CSP configuration in the SiP. In relative terms, the performance of the low reliability CSP configuration was significantly impacted by solder ball alloy while the performance of the high reliability CSP configuration was significantly impacted by the solder paste alloy. 
 

Flipchip Joining to Temperature Sensitive Flexible Substrates Using a Die Bonder with Asymmetric Heating
Authors:  Peter McClure, Mukund Ayalasomayajula
Abstract
        Being able to join bumped silicon chips to temperature sensitive flexible substrates is a key manufacturing enabler for the flexible hybrid electronics industry. Attachment of such devices using asymmetric heating applied with a die bonder was explored as a means to minimize the thermal load on temperature intolerant substrates. Chip joining with SnAgCu (SAC) solder, BiSnAg solder, and an isotropic conductive adhesive material were all demonstrated through the use of top side asymmetric heating. Polyimide, polyethylene terephthalate, and thermoplastic polyurethane substrates were examined for physical or chemical alteration from the thermal load of such bonding.
Key words: Asymmetric heating, PI, PET, TPU, ICA, BiSn, SAC, Die Bonder

Abstract
        With ever increasing power density in electronic packages, thermal management is critical to ensure reliable device operation within specification temperatures. Efforts are made to transfer heat efficiently between the heat source and the heat sink by reducing the thermal resistance. Thermal interface materials (TIMs) improve the efficiency of heat transfer by filling in between the asperities and air gaps of these two mating surfaces. In this study, four leading edge chip level TIM1s were evaluated. Characterization included measurement of unit area thermal resistance and thermal conductivity on metal rod samples.  Hardware performance was evaluated using two types of flip chip modules.  Thermal test chips were used to assemble test vehicle modules and Intel® Core™ i3 6100 functional processor modules were disassembled and rebuilt, with the four selected TIM1s as the thermal solution. The TIM1  was applied between the flip chip and the nickel plated, copper heat spreader. Thermal resistance was measured at time zero. Post assembly mechanical integrity of the thermal interface material was investigated using C-SAM (C-mode Scanning Acoustic Microscopy), cross-sectional analysis and SEM/EDX (scanning electron microscopy with energy dispersive x-ray). Improvement in time zero performance is reported for rebuilt processors compared to the existing thermal solution in Intel processors. Further process development is needed to optimize assembly process conditions for time zero and reliable thermal performance. 


Assessment of BiSn/SAC Mixed Assemblies: Microstructure and Strain Rate Sensitivity 
Author:  Luke Wentlent
Abstract
        The continued push of the electronics packing industry for less damaging reflow techniques has resulted in an increased interest in low-melting point solder alloys. While solder systems, such as eutectic Bi-Sn, offer significantly lower melting points (~139°C) they are not commonly used in the industry and there is a considerable deficit of reliability and mechanistic knowledge. Additionally, most BGA components come balled with SnAgCu solder spheres as it is the current industry standard. When low temperature BiSn eutectic paste is used in conjunction with the SAC, a mixed solder joint is formed of which the reliability and performance is relatively unknown. This study takes a first look at the reliability behavior of the BiSn(Ag)/SAC mixed assembly solder joints and identified the failure mechanisms and behaviors in accelerated thermal cycling.


VIPPO Type Failures in PCBs with Buried Vias 
Author:  Pericles Kondos
Abstract:
        A board with long buried vias in different locations relative to nearby pads was used to study a defect manifesting itself as a clean separation between the solder and the intermetallic layer of one of the pads (usually at the component side) after a second reflow, leaving a relatively smooth solder-side failure surface not mirroring the shape of the intermetallic. Because this defect has often been observed in PCBs that have a mixture of Via-in-Pad-Plated-Over (VIPPO) and non-VIPPO pads, it has been designated “the VIPPO defect”. It was found that the buried via location affected the incidence frequency of this defect as did some process parameters including the reflow atmosphere (air vs. nitrogen). One of these combinations seemed to have the best chance of completely eliminating the defect, although more experiments are needed to verify this conclusion.


BGA Reliability as a Function of PCB Pad Geometry
Author:  Michael Meilunas 
Abstract:
      Three daisy-chained Ball Grid Array (BGA) package designs were assembled to printed circuit boards (PCB) containing solder mask defined (SMD) and non-solder mask defined (NSMD) pad geometries using SnPb and SAC305 soldering processes. The samples were subjected to accelerated thermal cycling with in-situ monitoring in order to stress the assemblies in an attempt to generate solder joint fatigue failure. Failed specimens were then analyzed in order to determine failure mode and location and lifetime data was compiled and compared using Weibull plots.  The experimental results indicate that circuit board pad definition is an important factor affecting Ball Grid Array solder joint lifetime. Interestingly, the relative reliabilities of the BGA assemblies on SMD and NSMD PCB pads were found to be dependent upon both component selection and solder alloy.    


FEA of BGA Joint Stress as a Function of Die Size 
Authors:  Mahdi Farahikia, Peter McClure, Richard Coyle, Jim Wilcox
Abstract:
        Finite Element Analysis (FEA) was conducted to gain insight into stresses occurring during accelerated thermal cycling (ATC) in a large silicon die ball grid array (BGA) package.  This BGA package has exhibited a variety of atypical behaviors in previous studies.  For example, studies have reported failures in package corner joints as expected but with bimodal cracking along the printed circuit board (PCB) side of the joint.  When non-corner joints failed however they exhibited more traditional cracking along the component side of joint.  Beyond the cracking behavior, some studies have reported unexplained increased ATC lifetime with thermal aging.  These BGAs where built with abnormally large Si die to drive quicker failures in ATC testing.  It was thought that atypical stresses associated with this large die could be driving the unexpected failures/results.  To test this, a study compared this package under ATC with three different die sizes.  All die sizes exhibited the abnormal corner joint failure modes but the smaller die BGAs had an increased occurrence of non-corner joint failures with traditional cracking.  These results pointed to stresses changing with die size and possibly causing the atypical corner joint failures.  This study used FEA to examine the stresses in solder joints as a function of die size and joint location.  By modeling the three different die size packages under thermal cycle it was found that the atypical failure in corner joint correlated to large normal stress ranges seen in only in corner joints.  Additionally, increased die size was found to increase the relative stress concentrations of the normal stress range in corner joints; possibly correlating with the increase in non-corner joint cracking seen with smaller die.  

Key words:  FEA, BGA, Die Size, ATC, Normal Stress Range


        Ten large BGA (60mm) System in Package (SiP) configurations were evaluated for assembly issues and thermal cycle reliability performance. Dynamic warpage was characterized using Shadow Moiré interferometry and the shape profiles were used to analyze assembly yield defects.  Samples were subjected to -40 to 125C thermal cycling in order to stress the assemblies and drive solder fatigue failures for comparative reliability analysis. Failure locations were mapped for all configurations and select samples were cross-sectioned to examine failure mode. Weibull analysis was performed on all SiP BGA and CSP populations in an attempt to correlate reliability to SiP layout. The results of this experiment showed that memory placement, solder alloy, and underfill application all significantly impact the SiP BGA reliability.    
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