2017 Reports


Accelerated Thermal Cycling Lifetime and Failure Modes of Isothermally Aged SAC305 BGA Assemblies
Author:  Peter McClure
Abstract: 
        The effect of isothermal preconditioning (aging) of SAC305 solder on the characteristic lifetime under accelerated thermal cycling (ATC) was examined. Test vehicles with ball grid arrays (BGAs) attached to printed circuit boards (PCBs) using SAC305 were aged for either 0, 20, or 40 days at 125°C. After aging, the test vehicles were put into ATC test using either 0↔100°C or −40↔125°C cycles. It was found that aging increased characteristic lifetime, contrary to the expected decrease. Failure analysis (FA) of cycled parts showed anomalous cracking on the PCB side of solder joints with two modes of crack propagation. Analysis of the increased lifetime, FA, and possible causes for this anomalous behavior are discussed.
Key words: Aging, SAC305, ATC, Failure Analysis, BGA, PCB


Fine Pitch CSP Printing Analysis using NAMI and Fine Grain Stencils
Authors: Michael Meilunas, Jeff Schake
Abstract: 
        A solder paste print study was performed with 0.3 to 0.5mm pitch chip scale package (CSP) footprints. The study compared the effects of multiple stencil design and fabrication variables as well as solder paste selection and printing machine parameters.
        Circuit boards containing CSP footprints of various pitches and pad dimensions were acquired for the study. Solder paste was screen printed over the boards using nanocoated NAMI and non-coated fine grain stencils of 50 and/or 80 micron thickness. The paste deposits were inspected and measured with a Koh-Young ASPIRE and the volumetric data was compiled and analyzed. The process was repeated for three solder pastes which included type 4 and type 5 particle sizes and was performed with and without ASM DEK ProActivÒ vibratory squeegee action. The results of the experiment for the CSP footprints are discussed in this report. The data indicates that fine pitch solder paste printing can be successfully performed using the paste, stencil and printer technologies evaluated. However, stencil aperture design is a critical factor affecting the results and each combination of stencil parameter (i.e., material, thickness, coating), solder paste selection, component footprint (i.e., pitch, pad dimension) and squeegee action may require a specific aperture size for high yield assembly.


Authors:  Sai Srinivas Sriperumbudur, Martin Anselm, Michael Meilunas
Abstract
        Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards and it has been reported that a majority of all assembly defects occur during the stencil printing process.  It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as Land Grid Array (LGA) and Quad-Flat No-Lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The goal of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations.
        Stencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed in order to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using Solder Paste Inspection (SPI) system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield.  Accelerated Thermal Cycling (ATC) was used to determine the reliability of the solder joints.  Failure analysis was used to determine if the failure was attributed to the low paste volume locations.  Solder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices.  A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling.  

Author:  Peter McClure
Abstract
The effect of die to package ratio (DPR) on the reliability and cracking modes of chip array ball grid array (CABGA) packages under accelerated thermal cycling (ATC) was examined.  BGA packages with 1414mm molded bodies and made with either a 1212mm, 9.59.5mm, or 7.27.2mm silicon die, were subjected to ATC reliability testing with either a 0/100oC or -40/125oC cycling profile.  The largest die version of this BGA package has been used in several previous industry studies and given inconsistent and atypical results, with varying characteristic lifetimes and cracking modes reported.  It has been hypothesized that the large DPR of this BGA is leading to the unexpected and inconsistent results.  To test this hypothesis, this study examines the effect of die size on the reliability of the BGAs and cracking modes of the SAC305 solder joints.  It was found that the large DPR of the largest die BGA is not solely accountable for the inconsistent results or atypical solder cracking.  Comparison of Weibull failure rate statistics of the measured cycles to failures did not show any irregularities among the die sizes and similar crack morphologies were seen for all die sizes.  However, the largest die size had significantly less non-critical cracking than the smaller die BGAs, indicating a change in the stress distribution.

Authors:  Sai Sriperumbudar, Martin Anselm, Michael Meilunas
Abstract
        The goal of this experiment was to determine the acceptable lower limit for solder paste volume deposit tolerance during stencil printing processes to ensure both good assembly yield and reliability expectations with BGA and CSP componentry. The experiment was conducted with the assumption that the minimum acceptability limit for a BGA or CSP paste deposit is currently -50% of stencil aperture volume.  Based on this assumption, low-volume outliers in the range of -50 to -80% of stencil aperture volume were generated for assembly yield analysis and, ultimately, reliability analysis using accelerated thermal cycle testing. The results show that the low-volume outliers had no impact on the assembly and, contrary to traditional thought, had negligible impact on the accelerated thermal cycle reliability of the devices investigated.

Author:  Peter McClure
Abstract
        A variety of substrate materials are of interest to the flexible electronics industry.  Currently the workhorse substrate is polyimide (PI) which can withstand the thermal requirements of traditional convection oven solder reflow, so no special processing techniques are required.  But other substrates of interest are not thermally robust enough to endure traditional oven reflow.  Special processing techniques (low melt solders, conductive adhesives, alternative heating, etc.) are required.  Two such temperature sensitive substrates are polyethylene terephthalate (PET) and thermoplastic polyurethane (TPU).  In the case of TPU, oven soldering with SAC alloys is impossible because TPU will degrade during the process.  In this study, a preliminary exploration of the possible use of area Laser Selective Reflow (aLSR) to join wafer level chip scale packages (WLCSPs) to PI, PET, and TPU substrates with SAC or BiSnAg solders was conducted.  With aLSR preferential heating of solder can be achieved with short (<5sec) reflow time; significantly reducing the thermal load on substrates.  This work is focused on determining if WLCSPs can be attached, without damaging the substrates, with aLSR.  Different traces metallizations under aLSR were also examined; solid copper, silver ink, NovaCentrix ink, and Tatsuta ink.

Solder Void Formation in LGA and QFN Assemblies
Author:  Michael Meilunas
Abstract:
        LGA and QFN solder joint quality was evaluated for various convection oven reflow processes in order to determine which parameters, if any, affect the level of solder joint void formation. Parameters investigated included peak reflow temperature and reflow atmosphere. The experiment was performed with a standard no-clean solder paste and a paste marketed as a “low void” formulation. Assembled samples were inspected using x-ray imaging to determine void size and quantity for each process, component and paste combination.

        Ever greater performance demands on electronic applications continue to drive increased miniaturization, higher package density and novel materials that can exceed the limits of existing assembly manufacturing processes. Such new technologies are demanding a greater control over the solder reflow process while still maintaining a high production throughput. In order to meet these challenges, an area Laser Selective Reflow (aLSR) instrument was developed by Crucial Machines, the capabilities of which were studied at the UIC-Conklin process laboratory. This report describes the observations and insights obtained from detailed evaluation of the laser reflow process. The solder reflow behavior as well as solder interconnect quality were assessed. Subsequent consortium reports will focus on various process parameters that influence the laser assembly process

Author: Michael Meilunas
Abstract:
        Six large (55x55mm) BGA package designs were evaluated for assembly issues and thermal cycle reliability performance.  The BGA designs included three silicon die configurations with multiple thermal lid attachment configurations in addition to non-lidded samples.  Dynamic warpage was characterized using Shadow Moiré interferometry and the shape profiles were used to analyze assembly yield defects.  Samples were subjected to -40 to 125C thermal cycling in order to stress the assemblies and drive solder fatigue failures for comparative reliability analysis.  The experiment indicates that the die and lid configurations play a significant role at both the assembly and reliability level.

Author: Michael Meilunas
Abstract:
        A cyclic 4-point bend test method was utilized as a means for investigating printed circuit board pad cratering behavior for five different laminate materials:  Nelco 4000, Nelco 4800, ZetaCap, Meteorwave 1000 and I-Speed.     


Using Electrical Capacitance and Mechanically Representative Hardware to Evaluate the Thermal Mechanical Stability of Thermal Interface Materials

Authors: Michael A. Gaynes, Lauren Boston and Andrew Yu
Abstract:
    Experimental study of material performance is a necessary complement to virtual qualification efforts that use modeling and simulation to streamline development of new electronic assemblies. The durability of thermal interface materials in large complex printed circuit board (PCB) assemblies is difficult to model and therefore, experimental study and verification is needed. The thermal mechanical stability of dielectric thermal interface materials is monitored using electrical capacitance, the inverse of which has the same geometric dependence on bond line and area as thermal resistance. Electrical capacitance is fast, easy and accurate to measure and can be used with mechanically representative hardware very early in the development cycle. Four thermal interface materials (TIMs) classified as pre-cured thermal putties are evaluated on hardware that is easily prototyped and which is mechanically representative of large complex PCBs. Electrical capacitance of the TIMs was measured in situ during thermal cycle testing and could distinguish stability as well as degradation. Analysis of the TIMs after the test confirmed structural damage in the form of cracks, fissures and material movement. Electrical capacitance has broad application in evaluating the stability of dielectric TIMs in application specific designs very early in development by using easily procured mechanically representative hardware.


Abstract:
    With ever increasing power density in the electronic packages, thermal management has become critical to ensure device operation within specification. Efforts are made to transfer the heat efficiently between the heat source and the heat sink by reducing the thermal resistance. Thermal interface materials (TIMs) improve the efficiency of heat transfer by filling the asperities/air gaps between these two non-ideal mating surfaces.
    In this study, two silicone and one non-silicone thermal interface putty materials are evaluated. Characterization included measurement of unit area thermal resistance, thermal conductivity and dielectric constant, the latter of which is used in conjunction with electrical capacitance to calculate bond line thickness. The thermal interface materials were used between a thermal test vehicle and an aluminum heat sink. The target bond line was 0.5 mm and was achieved by pressing the heat sink down to 0.5 mm shims inserted at the corners between the heat sink and thermal test vehicle. Thermal resistance was measured at time-zero and at various points during thermal cycling between -40°C and 125°C: 250, 500, 750 and 1000 cycles. Increases in thermal resistance did occur. After thermal cycling the thermal test vehicle and heat sink were separated to observe the integrity of the thermal interface material. There was evidence of material degradation in the form of cracks and fissures. Accelerated thermal cycle testing was found to be very useful in assessing the impact from differential thermal expansion in electronic assemblies.

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