2016 Reports

Authors:  Marie Cole, Jacob Porter, Jason Wertz, Marc Coq, Jim Wilcox, Mike Meilunas
Abstract:
        Thick film resistors are used extensively in a variety of electronics applications.  The silver in a conventional thick film resistor is prone to the attack of sulfur-bearing gaseous contamination.  This problem has been documented for servers that are found in data centers, due to the environmental pollution of sulfur in certain industrial locations and more typically, in growth market countries where the use of coal to produce electricity is prevalent.  The growth of silver sulfide, resulting from silver corrosion, can cause an increase in resistance and eventually, an electrical open of the resistor.  The best method to increase the robustness of resistors in high sulfur environments is to employ Anti-Sulfur Resistors (ASR).  These resistors either have a structure alteration to seal the ingress path from sulfur bearing gases or use a noble metal for the resistor contacts.  Occasionally, unique resistor part numbers have limited availability in ASR construction.  Thus, it is beneficial to have alternate techniques to mitigate sulfur-induced corrosion.
        This paper will discuss the evaluation of conformal coatings to mitigate silver sulfide corrosion of thick film resistors.  Two-part epoxy has been demonstrated to prevent resistor corrosion, but has manufacturability concerns in high volume production.  Conversely, coatings that contain silicone are known to increase silver sulfide corrosion due to their inherent nature in readily absorbing sulfur.  Other conformal coating chemistries are available for various applications, but have not been tested for their ability to mitigate silver sulfide corrosion of resistors.  A Flowers of Sulfur (FoS) test procedure can evaluate the tendency for silver sulfide corrosion of resistors to occur as a predictor of field performance.  This technique was used to evaluate polyurethane and acrylic materials, in addition to a nanocoating.  Uncoated, epoxy-coated and silicone-coated samples were used as controls for comparison to the coatings evaluated.  Results and observed corrosion trends for a variety of resistor body sizes will also be discussed.


Authors: Mohammed Genanu, Francis Mutuku, Eric Cotts, Scott Pollard, Aric Shorey, Eric Perfecto, Babak Arfaei
Abstract:
        With the challenges of moving to 2.5/3D packaging structures, it has become imperative to improve our understanding of the materials science of fine pitch Pb-free solder joints. The use of Cu pillars capped with thin layers of SnAg solder provides for tighter bump pitches reducing the chance of solder bridging at chip joining. However, changes in geometry, materials and processes associated with 2.5D packaging create new materials challenges.  The thinner solder regions mean that a larger volume fraction of joints is consumed by the formation of intermetallic compounds at the pillar/SnAg solder interface. The final concentration of Ag in the joint can vary, and the Ag3Sn precipitate morphology in the solder joint may change, directly affecting the reliability of the joint. This can occur through the formation of Ag3Sn plates, or simply because of different distributions of much smaller Ag3Sn precipitates.  Or, the entire solder joint may be transformed into intermetallic compounds during assembly or operation of fine pitch joints. The presence of interposer materials with a different CTE compared to FR-4 laminates may also affect the lifetime of the package during drop/shock or thermal fatigue. 
        In the current study, relations between processing, microstructure and reliability of assemblies enabled through Cu pillar/interposer technology were examined. The effects of solder cap composition, thickness and volume on microstructure of assemblies on Si and glass substrates were examined. Effects of multiple reflows on the microstructure of solder joints were also studied. Significant variation in Ag3Sn precipitate morphology was observed under nominally identical fabrication conditions. These were correlated with relatively large variations in mechanical behavior, for instance in measured values of shear strength. Large variations in Ag3Sn precipitate size and number were also observed with changes in composition and upon aging, as would be expected. Cu pillar assemblies revealed small, but continuous solder layers. After failure during ATC, cracks were found to have propagated through these continuous solder layers.


Author: Harry Schoeller
Abstract: 
        With electronics being integrated into higher temperature environments such as those associated with deep well drilling and distributed controls for “under the hood” automotive applications, higher melting temperature solders are needed. While limited data on bulk high temperature solders is available, data on joint level behavior is woefully lacking.  Further, the data presented is often measured at room temperature and cannot be extended to higher service temperatures where the solders are actually used.  In this work, a test methodology was developed for high temperature isothermal shear fatigue of individual solder joints. A total of six solder alloys, five Pb-based alloys and one Pb-free alloy were tested at 25°C and 200°C.  Joints tested at 200°C were first stored at 200°C for 1000 hrs to measure performance in a simulated high temperature environment.   The microstructure was studied in conjunction with the fatigue results to understand the structure-property-performance relationship. Result show those alloys with a dendritic structure had a greater characteristic life at room temperature.  At 200°C coarsening of the microstructures led to dramatically different results.   

Authors:  Sai Sriperumbudur, Martin Anselm, and Michael Meilunas
Abstract:
        Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as Land Grid Array (LGA) and Quad-Flat No-Lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The goal of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations.
        Stencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed in order to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using Solder Paste Inspection (SPI) system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield.  Accelerated Thermal Cycling (ATC) was used to determine the reliability of the solder joints.  Failure analysis was used to determine if the failure was attributed to the low paste volume locations.  Solder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices.  A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling.  
        Very little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50% or ±30% of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.


Broadband Printing II: Step Stencil Design Evaluations
Author:  Michael Meilunas
Abstract:
        Broadband printing is the term often applied to an electronic assembly process in which both fine and large pitch componentry is assembled through a stencil printing process. Broadband printing applications may require step stencils in order to effectively deposit solder paste over both large and small features. Step stencil design guidelines may be found in IPC-7525B, which was released in 2011. The standard includes recommendations for minimum step edge to aperture spacing and, by extension, minimum step region width. In the ensuing years, significant advances in step stencil fabrication and solder paste technology have occurred, potentially allowing for even tighter step edge to aperture spacing and ultimately, furthering the miniaturization of electronic assembly. The following report describes an experiment which utilized a 120 micron thick stencil with 20 and 45 micron thick step downs of varying width and multiple step edge to aperture spacing, including distances which were significantly less than IPC-7525B recommendations. Multiple print processes were used to screen a type 4.5 solder paste over test boards which were then examined using an automated solder paste inspection system to collect solder paste area and volumetric data. Data analysis was performed to determine which designs and process factors resulted in acceptable printing.
 
Thermal Cycling Reliability of Underfilled Assemblies on TB2013
Author:  Pericles A. Kondos
Abstract:
        Four different underfills from various suppliers were used to underfill many different types of components on the front side of the main section of TB2013 test boards. The process details have been described in previous reports. The assemblies were subjected to accelerated thermal cycling (ATC) and the results are presented here together with failure analysis. The main purpose of this project was to compare the ATC performance of each underfilled component type with that of the non-underfilled, but comparison between underfills was attempted too. It was found that no underfill was consistently better across the board, although some trends did emerge.


Effect of Low Volume Solder Paste Deposit Outliers on BGA/CSP Assembly and Reliability Expectations
Authors:Sai Sriperumbudar, Martin Anselm and Michael Meilunas
Abstract:
      The goal of this experiment was to determine the acceptable lower limit for solder paste volume deposit tolerance during stencil printing processes to ensure achieving both assembly yield and reliability expectations with BGA / CSP componentry. The experiment was conducted with the assumption that the current minimum acceptability limit for a BGA or CSP solder paste deposit is -50% of stencil aperture volume. Based on this assumption, low-volume outliers in the range of -50 to -80% of stencil aperture volume were generated for assembly yield analysis and ultimately reliability analysis using accelerated thermal cycle testing. The results show that the low-volume outliers had no impact on the assembly and, contrary to traditional thought, had no negative impact on the accelerated reliability of the devices investigated.

Evaluation of PariPoser Anisotropic Conductive Elastomer
Author: Michael Meilunas
Abstract:

    This report documents the characterization and reliability evaluation of PariPoserTM, a thin, electrically conductive film designed for electronic packaging interconnects and may be used as a substitute for surface soldering in some applications.

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